1. Field of the Invention
This invention relates to a process for preparing a semiconductor device.
2. Related Background Art
Process for forming the emitter region of a bipolar transistor has the two steps of window opening, such as window opening of emitter diffusion region, impurity diffusion, window opening for electrode withdrawal, electrode formation.
Accordingly, in recent years, as the device is made finer, self-matching technique which forms window opening at one time has been actively studied, and particularly the technique by use of a polycrystalline silicon containing an impurity (Doped Poly-Si:DOPOS) is general.
More specifically, as the bipolar transistor (BPT) best suited for effecting shallowing of junction and high integration, DOPOS BPT of a polycrystalline silicon emitter which can prepare an emitter according to the self-align process has been known.
Such DOPOS BPT is used also as the wiring element, and as the method for injecting an impurity into a polycrystalline silicon, there is the ion injection method.
After an impurity has been injected according to the ion injection method into a polycrystalline silicon, heat treatment has been practiced for activation at 900.degree. C. to 1000.degree. C. However, for accomplishing further fine formation of the element and shallowing of the semiconductor coupling, the heat treatment temperature is required to be made lower, and for example in the process corresponding to the minimum line width 0.5 .mu.m, a low temperature process of 800.degree. to 900.degree. C. has been employed.
Also, in the ion injection method of the prior art in which an impurity is injected into a polycrystalline silicon, because the ion injection conditions and the heat treatment temperature after injection are not optimum, there is the problem that the electrical resistance of the polycrystalline silicon obtained becomes larger (sheet resistance becomes larger). Particularly, this influence is marked in the low temperature process aiming at shallowing of junction.
Further, in the technique as described above, there ensue problems in progressing further finer formation of the device.
One problem is that, as the window opening dimensions are made finer, when an impurity is attempted to be introduced in the step after coating of the polycrystalline silicon, introduction of the impurity exhibits dependency on the window opening dimensions. This is described by referring to FIG. 1.
As shown in FIG. 1, when there are two kinds of transistors with different window opening dimensions, as finer formation is progressed, it may sometimes take place that the distances from the surface of the polycrystalline silicon 123 to the substrate (for example, l.sub.1 and l.sub.2 in the Figure) are different. For this reason, the width of the diffused layer (emitter region 111) formed on the substrate side will change from the desired one, whereby there is the problem that the characteristics of the transistor obtained become nonuniform.
FIG. 2 is a sectional view of the substrate when the diffused layer is formed in the Si substrate for illustration of the preparation process of the semiconductor device as described above. In the Figure, 201 is an Si monocrystalline substrate (hereinafter referred to as substrate), 202,203 are diffused layers, 210 is a polycrystalline Si deposited layer, and 210A a crystal grain boundary (hereinafter referred to as grain boundary).
The diffused layer 202 is formed by injecting directly an impurity into the substrate 201 before formation of the polycrystalline deposited layer 210, and the diffused layer 203 formed by injecting the impurity through the polycrystalline Si deposited layer 201.
That is, the diffused layer 203 is formed by injecting first an impurity into the polycrystalline silicon deposited layer 210 by ion injection, and thereafter diffusing the impurity from the polycrystalline Si deposited layer 210 into the substrate 201 by the heat treatment.
However, the diffused layer 203 thus formed by the method of the prior art, as shown in the Figure, has for example a deep junction 210D formed in the junctioned region 210B between the substrate 201 and the crystal grain boundary 210A. Accordingly, the junctioned face as a whole becomes nonuniform. This may cause variance in collector current and current amplification ratio in the case of the bipolar transistor in an integrated circuit.
Further in this method, a naturally oxidized film (ca. 5.ANG.) is formed between the substrate 1 in the step of depositing the polycrystalline Si, and the oxidized film may be partially destroyed by the heat treatment in the impurity diffusion to the substrate 1. This may cause the effective diffusion distance of small number of carriers injected into the emitter to be changed depending on the respective places in the emitter when the emitter junction is shallow, whereby variance of base current may be caused. In either case as mentioned above, the junctioned face is caused to become nonuniform, and this is a particularly important problem when the circuit formed on the substrate is highly integrated to make the thicknesses of the emitter layer and the base layer thinner.
Thus, as the higher densification and speed-up of actuation for semiconductor devices are demanded, fine formation of semiconductor device is under rapid progress. As a typical fine formation technique, the self-matching technique such as DOPOS (Doped Poly-Si) process, etc. as described above has been particularly widely applied. Whereas, as mentioned above, when the DOPOS is used as the diffusion source, many problems are accompanied. For example, there may sometimes ensue such problems as follows: (1) due to grain boundary diffusion accompanied with polycrystalline silicon, the diffused layer becomes nonuniform; (2) naturally oxidized film exists at the interface between polycrystalline silicon and monocrystalline silicon; (3) channeling occurs when an impurity is ion-injected into polycrystalline silicon; (4) resistance value is large as the property of polycrystalline silicon. In order to avoid such problems, a self-matching technique by use of a monocrystalline silicon in place of polycrystalline silicon has been also developed.
However, a monocrystalline silicon can be formed only on a monocrystalline silicon, and since the technique of growing a monocrystalline on Si/SiO.sub.2 is still insufficient, when a monocrystalline region is desired to be obtained sufficiently, there is the problem that finer formation and lowering of temperature can be effected with difficulty. What inconveniences will be caused to occur in practical IC and devices by such problems will now be shown by referring to the emitter diffusion of bipolar transistor as an example.
(1) Nonuniformization of the diffused layer means the change of the base width, which brings about nonuniformity of current gain ratio (h.sub.FE). This is vital to IC for which pairing characteristic is regarded as important.
(2) Presence of naturally oxidized film makes base current unstable, which is also a cause for nonuniformity of h.sub.FE.
(3) The problem of channeling is vital to shallowing of diffused layer, but since it is difficult to control channeling itself, nonuniformity of depth of emitter diffused layer occurs, whereby h.sub.FE becomes nonuniform.
(4) Polycrystalline silicon in itself becomes higher in resistance value as compared with monocrystalline silicon, which is unavoidable as long as a polycrystalline silicon is used. If the emitter resistance becomes higher, the current becomes insufficient, leading to lowering of driving capacity.